## Introduction

Phase-locked loops (PLLs) are widely used to recover the frequency of a carrier signal in many detection systems such as lock-in amplifiers and data receivers. In order to properly lock to the carrier phase and extract its frequency, a clean reference separate from the signal or a pilot tone within the signal must be provided for the PLL. However, there are application areas where such a clean reference is not available, for instance,

• Double side-band suppressed-carrier (DSB-SC) modulation systems where only the side-band components are present in the signal and the carrier is absent [1].
• Phase modulated (PM) signals such as phase-shift keying (PSK) and quadrature amplitude modulation (QAM) systems where the phase of carrier is time-varying [2].

In both cases, the PLL is not able to lock because there is no signal in suppressed-carrier systems and there is no stable phase in phase-modulated signals. In order to retrieve the carrier frequency of these systems, one approach is to use the so-called Costas loops which extend the standard PLLs by adding nonlinear and/or arithmetic operations such as multiplication and limiter to the feedback loops, [3] and [4].

In this post, first we look at the most common Costas loop which is used to recover the carrier frequency of DSB-SC and binary PSK systems. Then, we demonstrate how to implement this loop using the UHFLI Lock-in Amplifier and its PID Controller option and Arithmetic Unit feature.

## DSB-SC

Double side-band (DSB) modulation is a common modulation scheme used in many digital and analog systems. DSB-modulated signals contain 3 frequency components as follows.

• A carrier at frequency $$\omega_c$$
• A lower sideband at frequency $$\omega_c-\omega_m$$
• An upper sideband at frequency $$\omega_c+\omega_m$$

Were $$\omega_c$$ and $$\omega_m$$ are called carrier and modulation frequencies, respectively. In some applications, the carrier component is removed from the signal. This kind of signals is called double side-band suppressed-carrier (DSB-SC) modulation. The following expression describes a DSB-SC signal.

$s(t) = A_l \sin((\omega_c – \omega_m)t + \phi_l) + A_u \sin((\omega_c + \omega_m)t + \phi_u),$

where $$A_l$$ and $$A_u$$ are the amplitude of lower and upper sidebands, whereas $$\phi_l$$ and $$\phi_u$$ represents the phase of lower and upper sidebands, respectively. Figure 1 compares the spectrum of a DSB with a DSB-SC signal for a carrier frequency of 100 MHz and a modulation frequency of 1 MH.

Fig. 1. Spectrum of amplitude modulation (AM) signals: DSB with a carrier at 100 MHz and sidebands at 99 and 101 MHz (top), DSB-SC with only sidebands at 99 and 101 MHz.

Using the PID/PLL option of UHFLI lock-in amplifier, we can recover the carrier frequency of a DSB signal as long as the PLL bandwidth is much less than the modulation frequency. However, it is not possible to extract the carrier frequency of a DSB-SC signal using the PLL regardless of its PID parameters and filter bandwidth as shown in Figure 2. Using the AM/FM Modulation option of UHFLI we generate a DSB modulation at Signal Output 1 and a DSB-SC modulation at Signal Output 2 as described in [1] and [5]. Both outputs are looped back to Signal Inputs 1 and 2, respectively, for carrier recovery by PLL. The first PLL can easily lock oscillator 4 (green flag in Fig. 2) to the carrier of DSB modulation at Signal Input 1. However, the second PLL is not able to lock oscillator 8 (red flag in Fig. 2) to any signal around the carrier frequency of DSB-SC modulation at Signal Input 2.

Fig. 2. Lock-in tab of LabOne user interface showing 2 types of modulation signals, i.e. DSB and DSB-SC at Signal Outputs. PLL of oscillator 4 extracts the carrier frequency of DSB at Signal Input 1 properly, whereas PLL of oscillator 8 is unable to lock to the DSB-SC modulation at Signal Input 2. Click on image to enlarge.

In the next sections, we will see how the Costas loop can overcome the limitation of PLL in retrieving the carrier frequency of DSB-SC signals.

## Costas Loop

Before analyzing the Costas loop let’s look more into the DSB-SC signal $$s(t)$$ described by the formula given in the previous section. The signal has the following frequency components:

• Upper sideband with a time-varying phase $$\theta_u(t)=(\omega_c +\omega_m)t+\phi_u$$
• Lower sideband with a time-varying phase $$\theta_l(t)=(\omega_c -\omega_m)t+\phi_l$$

The goal of the Costas loop is to generate a carrier with a time-varying phase $$\theta_c(t)$$ which is the average of $$\theta_u(t)$$ and $$\theta_l(t)$$. In other words,

$\theta_c(t)=\frac{\theta_u(t) + \theta_l(t)}{2} = \omega_c t+\phi_c$

where $$\phi_c=(\phi_u+\phi_l)/2$$. Figure 3 shows the scheme of the Costas loop used in this blog post. The main difference between this Costas loop and the standard PLL is in the feedback branch where a multiplicative operator and a low-pass filter are applied to the demodulated signals before the PID controller.

Fig. 3. Block diagram of the Costas loop which has a multiplicative operator before its PID controller compared to a standard PLL system.

The main idea behind the multiplication in the feedback line is to provide a baseband error signal out of the bandpass I and Q signals for the PID controller. Since both I and Q signals are at $$\omega_m$$, after multiplication and filtering, a DC component is obtained to apply to the PID controller as an error signal. Then, the PID controller applies a feedback signal to the voltage-controlled oscillator (VCO) or numerically-controlled oscillator (NCO) to adjust its frequency and phase. Suppose that the VCO/NCO generates a signal with a time-varying phase $$\theta_0(t)=\omega_0 t+\phi_0$$. The aim of the Costas loop is to control the VCO/NCO in a way that its output phase is identical with the phase of the received signal’s suppressed carrier, i.e. $$\theta_0(t) = \theta_c(t)$$.

Assuming a gain of $$\sqrt{2}$$ for the low-pass filter after the multiplier, the error signal applied to the input of PID controller can be described by the following expression:

$e(t) = A_u A_l \sin(2(\theta_c – \theta_0))$

This equation shows that the error signal is a monotone and nearly linear function of the phase difference when the system is close to lock, i.e. $$\theta_c\approx\theta_0$$. In other words, the error signal is proportional to the phase difference between the signal carrier and the local oscillator.

$e(t)\propto 2[\theta_c(t) – \theta_0(t)]$

Moreover, the factor 2 applied to the phase in the above equations shows that the error signal is twice sensitive to the phase difference compared to a standard PLL. After receiving the error signal, the PID controller adjusts the phase and frequency of VCO/NCO such that the oscillator phase $$\theta_0(t)$$ follows the carrier phase $$\theta_c(t)$$.

## Implementation

In this section, we implement the Costas loop illustrated in Fig. 3 using the UHFLI Lock-in Amplifier. The Arithmetic Unit (AU) of the instrument is the key tool to obtain the product of in-phase and quadrature signal components I and Q after demodulation.  Moreover, the device PLL/PID option is used to implement a proportional-integral (PI) controller to adjust the phase and frequency of the instrument’s oscillator according to the error signal obtained by the AU. In order to decouple the signal generation and the Costas loop, we use another instrument to generate a DSB-SC signal which has two sidebands at 19 MHz and 21 MHz with a suppressed carrier at 20 MHz. This signal is applied to the input of UHFLI and there is no other signal available from the signal generator to provide a reference. The goal of the experiment is to recover the signal carrier at 20 MHz for proper demodulation.

Figures 4 and 5 show the settings required to implement the Costas loop. First of all, the received signal must be demodulated by the local oscillator of the instrument which is shown in Lock-in tab of user interface in Figure 4. This local oscillator will be finally controlled by the PI controller when the feedback loop is closed.

Fig. 4. Instrument settings: Lock-in tab (top) and Aux tab (bottom) of LabOne. Important settings are highlighted with red boxes. Click on image to enlarge.

After demodulation, the signal components I and Q, or equivalently, X and Y, are multiplied using the AU as shown in the Arithmetic Unit tab in Figure 5. According to the block diagram in Figure 3, the result of multiplier should be filtered to obtain the baseband error signal. The trick here is to send the AU output to one of the Aux Outputs as shown in the Aux tab of Figure 4, and then, to demodulate the corresponding Aux Output at DC as depicted in the Lock-in tab of Figure 4. Aux Out 1 is assigned to demodulator 5 where its frequency is set at 0 by oscillator 2. This way, the AU output is low-pass filtered and the error signal is obtained at the Y component of demodulation at DC.

Fig. 5. Instrument settings: Arithmetic Unit tab (left) and PID/PLL tab (right) of LabOne. Important settings are highlighted with red boxes. Click on image to enlarge.

As depicted in the PID/PLL tab of Figure 5, the PID controller receives the error signal which is actually the Y component of demodulator 5 and then controls the frequency of oscillator 1 around the center frequency 20 MHz. The P (Hz/V) and I (Hz/Vs) parameters are obtained based on the level of error signal and required shift in oscillator frequency. The PID advisor of LabOne can help to estimate the controller parameters.

To verify that the implemented Costas loop can follow the carrier frequency of DSB-SC signal, we sweep the frequency of the signal generator within a certain range, here 10 kHz, around the carrier frequency 20 MHz. Then, we measure the frequency of the receiver oscillator controlled by the PID of the UHFLI instrument. Figure 6 shows the carrier frequency obtained by the Costas loop as the signal generator sweeps its frequency in a bidirectional mode.

Fig. 6. Carrier frequency of the received DSB-SC signal extracted by the Costas loop as the signal generator sweeps its frequency.

The error signal applied to the input of the PI controller is illustrated in Figure 7. It clearly shows that when the controller is in its steady state, the error signal is at 0 V, whereas it enters its transient behavior as soon as the signal frequency changes.

Fig. 7. Extracted carrier frequency (red) and the error signal (blue) which shows a steady level at 0 V when frequency is stable.

Figure 8 depicts the frequency shift around the center frequency which is determined by the PID shift. Moreover, it shows the PID error which has exactly the opposite sign of the error signal entering the PID controller because the PID setpoint is at 0 V.

Fig. 8. Frequency shift (green) generated by the PID as well as the error signal (blue) entering the PID and the PID error (red) showing the exponential behavior of the entire feedback loop.

The time-constant of the exponential decay in the PID error signal determines the speed or bandwidth of the Costas loop. This can be adjusted by tuning the PID parameters.

## Conclusion

In some applications where a phase-stable reference signal is not available, standard PLL systems fail to lock to the signal frequency. Costas loops can overcome this limitation in certain areas such as phase-modulated or suppressed-carrier signals. Thanks to its arithmetic unit, PID controller, and multiple demodulators, the UHFLI Lock-in Amplifier is a unique tool to implement a fully-digital Costas loop in one instrument. With a frequency range up to 600 MHz and a demodulation bandwidth up to 5 MHz, the device can cover a broad range of carrier and modulation frequencies.