Pass/Fail Tests for Failure Analysis

For quality control in manufacturing process, there are many ways to tests for transistors or other component failure, but for high throughput verification usually simple Pass/Fail tests are required. Since devices are tested for various functions, different tests need to be performed in this pass or fail mode. The basic principle always require a pulse shot to be triggered for predefined conditions such as an amplitude threshold, a phase delay, or more generally a voltage mismatched to an expected voltage response.

As a broader approach, the Reader can also see this blog as an example use of the UHF-DIG Digitizer option, which describes sophisticated triggering scheme from internal signals or over certain time window. Most tests and examples described here can be reproduced by Zurich Instruments Users with the following configuration:

1. Typical Pass/Fail scenarii

In order to better illustrate some typical case, 4 Pass/Fail examples that require different triggering scheme are shown below. On this first figure, change in amplitude or phase, as detected from a lock-in amplifier, is enough to trigger a Pass/Fail condition.

PassFail 12

Figure 1: Pass/Fail analysis – Lock-in technique

For highly non-harmonic signals, or for condition that require triggering only over a certain time window, it necessitates a different approach. To some extent, it may look like a Boxcar technique (i.e. define a time window to record data and discard everything else), except that only a single pulse, or shot, needs to be analyzed, and not averaged over several cycle, hence the need for fast digitization. This particular option is therefore only available with the UHF-DIG Digitizer and come along with 2 simultaneous scope traces. The figure below looks at truncated event or missing bits inside a certain sequence.

PassFail 34-new

Figure 2: Fass/Fail analysis – trigger gating

Now that we identified different event categories that needs to be discriminated as pass or fail, the actual output should be ‘0’ or ‘1’, which as a logic gate will look like a TTL pulse.

2. How to generate TTL pulse from triggered event ?

This is a fairly new feature, available from LabOne 15.01 Release, so please upgrade from the Downloads page if you do not see it in your current release.

As a simple example, let’s generate a sine-wave from Output 1 to Input 1, or a Triangular shape (from Osc φ Demod X) to mimic a ramp. In the Scope tab, one can ‘Show level’ for the trigger and move it to a desired threshold. This allows having a triggered wave that remains stable on the scope display. But it can also be used as input level for the ‘Scope Trigger’ in the DIO tab as shown here:

TTL pulse from scope trigger

Figure 3: Generating TTL pulse from Scope trigger

Such TTL pulse will be generated each time the condition on the scope trigger level is met. In the case of a periodic sinewave, we end-up with a periodic train of pulses but it all depends on the original signal from which the trigger level is taken from. For instance, if we test a voltage ramp to a certain threshold, only the ramps that reach that threshold will trigger an event and all other discarded.

NB: For internal scope visualization, an attenuator is required on Input 2 because the 3.3V TTL pulse exceed the UHFLI Input range. If you do not have access to the 2 scope traces or have no attenuator, then you need an external oscilloscope to visualize the actual pulse shape.

3. Cross-domain triggering with Arithmetic Units

By cross-domain triggering, we mean that any signal from time or frequency domains can generate a trigger event, which can then synchronously capture data across the whole signal panel, either internal, external or realtime computation of internal signals.

The Scope Trigger only works to discriminate signal levels (vertical axis), so for event that are time dependent (horizontal axis), such as a difference of phase or delay, it is necessary to first measure this delay and then send it to the Scope for advanced triggering capability. All internal signals, as well as all signals generated from the Arithmetic Unit, can be visualized with the internal Scope. In the screen capture below (click to see the complete LabOne screen with more tabs), we used AU Polar 1 as Scope Input with a rising edge. AU Polar means the results from the computation of the Arithmetic Unit in Polar coordinate, which in this case was simply the difference of Demod φ1 –  Demod φ2. This signal was internally generated from the beating of Oscillators 1 & 2, as a reference signal for our example.

Cross-domain AU

Figure 4: Cross-domain triggering on difference of phase as computed from the Arithmetic Unit (Click for more details)

Again, the Scope trigger level serves as a source for the DIO drive which in this example shot 2 TTL pulse on a Rising edge when the calculated phase difference pass this level. In this example, a Trigger gating is also used, which will be explained in more details in the next paragraph.

4. Gated trigger for targeted events

One last case that still need to be considered for a general outlook is: how can one discriminate triggering events only occurring during a certain time window ? The answer is Trigger gating. Such gate can be either provided externally from a clock or internally and corresponds to case #3 & 4 in figure 2 above. First let’s look at how one would connect a typical experiment, where the reference is coming from an external source.

Connection diagram AWG

Figure 5: Connection diagram from and to the UHFLI

From this figure, we see that both Ref/Trigger 1 & 2 channels are used: the first one to define the TTL pulse for the Pass/Fail output and the second one to define the gate which is then re-injected through Aux Input 3. The later will be used as Trigger gating in the Scope as well. In the LabOne UI, we use Input 1 to detect the repetition rate (ExtRef on Signal In 1) and the signal of interest as seen in the Scope channel 1. Channel 2 is used to check the actual pulse shape, and in the case of the Trigger gating, the correct time window (phase adjusted) as compared to Input 1.

Gate experiment 1

Figure 6: Gating experiment, first define the adequate gating window (here at 1/3 of actual repetition rate)

Once the triggering condition are correctly adjusted, especially the phase to define the correct start and stop time, we can display the actual TTL pulse in the Scope instead and enable the Trigger gating to select ‘Trigger In 3’ (high or low level). This pulse is generated in the same way as described in section 2, but will be triggered only for events happening within the gating window as defined by Ref /Trigger DIO 2.

Gate experiment 2

Figure 7: Final setting overview with actual TTL pulse for every Pass condition. The light blue square wave only represents the actual gating window as used by the scope and defined from the previous screenshot

In the figure above the condition is met every time from a repetitive input signal, and we therefore end-up with a periodic TTL pulse, but in real-condition, the TTL pulse would be shot only at single events, either Pass or Fail.

Conclusion

This blog was intended to illustrate the adequate testing capability of the UHFLI, even for non lock-in applications. Fast streaming of data and digitization of single events with the UHF-DIG option allowed sophisticated triggering scheme to be implemented, among the whole panel of internal signals available and even computed via the Arithmetic Unit. A few examples in the domain of Pass/Fail testing were explained, which can then be reproduced for many different configurations.

Acknowledgement

I am grateful to Philippe Lentrein and Thierry Parrassin from STMicroelectronics for constructive discussion and explaination of the various configurations useful for Pass/Fail and other Failure Analysis requirements

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